1. Field of the Invention
The invention relates to a circuit and method for protecting the minimum run length in RLL code, and more specifically to a protection circuit and method using three states (Before, Turning, and After) to compute the valid path satisfying the minimum run length limited in RLL code.
2. Description of the Related Art
In general, an optical disk driver uses a slicer to convert RF signals into EMF (Eight to Fourteen Modulation) signals. Because the RF signal usually includes noises, the slicer sometime generates error EMF signals. For example, the minimum run length limited of EFM signal is 3T, but an error EFM signal may be only 2T or 1T. Therefore, a protection circuit is needed to restore the error EFM signal of 2T or 1T to a correct EFM signal with 3T. Currently, a Viterbi decoder is used to decode the correct EFM signal.
According to the Viterbi algorithm, it is necessary to compute the signal information contained in each survive path in order to generate total path metrics. At last, the survive path with minimum total path metric is selected to serve as a correct path, and then the correct EFM signal is found by way of reverse-derivation. However, when the CD/DVD optical disk driver system does not utilize the A/D converter but the slicer to convert the RF signal into the EFM signal, the information of the system with respect to the RF signal is focused on the zero crossing point. At this time, even though the decoder used by the Viterbi algorithm may still be included, many elements in the decoder are not be used. Consequently, the unused elements in the decoder can be eliminated from the original Viterbi decoder, thereby lowering the cost thereof.
In view of the above-mentioned problems, an object of the invention is to provide a simplified circuit and method for protecting the minimum run length in RLL code, wherein the minimum run length is protected by founding the optimum path according to the metrics of the states and other information at the zero crossing point (Turning), before the crossing point (Before), and after crossing point (After).
To achieve the above-mentioned object, a circuit for protecting minimum run length in RLL code is provided. The circuit operates in three states before, during, and after turning of the RF signals to find the optimum path to protect the minimum run length in RLL code. The protection circuit includes three state processors, a metric computing unit, a timing control unit, and an operation unit. Each of the state processors includes a decision bit, an invalid bit, a metric bit, and bit arrays of survive paths, and operates according to the control signals of before, during, and after turning states. The metric computing unit computes metrics of the EFM signals with respect to the turning states of before, during, and after. The timing control unit generates the control signals according to the EFM signals and outputs to the three state processors and the metric computing unit. The operation unit controls the decision bit, the invalid bit, the metric bit, and the bit arrays of survive paths of the state processors according to the control signals generated by the timing control unit and the three metrics computed from the metric computing unit, and generates correct output signals.
Consequently, the invention finds the optimum path to protect the minimum run length in RLL code by the tree state processors in conjunction with the limitations of the three turning states of during, before, and after.